Programmable integrated circuits are known in the art and include programmable logic devices ("PLDs"), Programmable Array Logic ("PALs"), and Programmable Logic Arrays ("PLAs"). Each of these programmable circuits provides an input AND logic plane followed by an OR logic plane. An output function comprising the sum of the products of the input terms can thus be calculated. The logic planes are usually programmable such that the initial general layout of the planes may be customized for a particular application.
A more general approach to programmable circuits involves providing an array of distinct, uncommitted logic cells in a Programmable Gate Array ("PGA"). A programmable interconnect network is usually provided to interconnect the cells, and to provide data input to, and output from, the array. Customization or programming of the otherwise generally-designed logic cells and interconnect network is performed for a particular application. One such array is a Mask Programmable Gate Array ("MPGA"), in which the configuration of the cells and the wiring network occurs when adding the final layers of metallization to an integrated circuit. A modified approach involves the use of laser-directed energy to customize the metallization pattern. Another such array is a Field Programmable Gate Array ("FPGA") in which the configuration can be performed by a user, in the "field." Such configuration may be effected by using electrically programmable fusible links, antifuses, memory-controlled transistors, or floating-gate transistors. All of the above referenced types of programmable logic integrated circuits are referred to herein as "programmable arrays."
In an implementation of an FPGA using Static Random Access Memory ("SRAM") cells to hold configuration information, at system power-up/initialization the FPGA reads in the configuration information to the SRAM cells from an external source. More specifically, (FIG. 1) a state machine 17 within an FPGA 13 reads a parallel or sequential programming bit stream from a Read Only Memory ("ROM") 11 external to FPGA 13. The programming bit stream is read into the FPGA over data path 23 and is appropriately directed to individual programming cells of each logic cell 19 within the FPGA over data path 21. Conventional control communications are implemented between RAM 11 and state machine 17 to facilitate the data transfer. As is well known, FPGAs contain an array 15 of logic cells 19 interconnected by horizontal and vertical interconnects 25. These horizontal and vertical interconnects 25 comprise inter-cell programmable routing resources which facilitate communications between logic cells.
Connected within each logic cell 19 of the FPGA is a programming word 31 (FIG. 2). This programming word includes the above-described programming cells as bits (33a-33h) therein. Although, as an example, an 8 bit programming word is shown, programming words may comprise 1.times.N (N&gt;1) bit register structures, wherein N is sized as needed to adequately control the logic cell. Once a programming word 31 is loaded, coupling between the individual bits thereof, the programmable logic 27 and the programmable routing resources 29 facilitates control of the configuration of logic cell 19. Programmable logic 27 and programmable routing resources 29 are interconnected by data paths 35. In some implementations, the programmable routing resources may be located external to logic cells 19.
Conventional logic cell 19 can only be used for a single programmed function at a time. Reconfiguration of the logic cell requires reactivation of the state machine and rewriting of the programming words. Such reprogramming during functional operation of the FPGA is possible, but requires relatively large delays and at least partial disruption of operations of the particular logic cell being reloaded.
Although FPGAs are more flexible than their prior mask programmed counterparts, even moderately complex logic functions can only be implemented using large silicon areas. This results from the data-flow oriented nature of FPGAs. Specifically, data is passed from programmed logic cell to programmed logic cell with a preprogrammed logic function applied at each logic cell. Because each logic cell has a large overhead for providing a single programmed function, not to mention the large overhead associated with the programmable routing resources, overall FPGA logic densities remain low. Furthermore, these conventional datapath-oriented implementations suffer penalties in the areas of timing and performance due to inconsistencies in signal routing for different bits in the datapath.
The present invention is directed toward solving the above-noted problems.